| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device of which a lowering in yield can be evaded by securing an appropriate cell property margin even though the cell property is deteriorated with a lapse of time or change of the operation environment. <P>SOLUTION: This device is equipped with: a memory cell having such a circuit configuration that potentials to be supplied to sources of load transistors 108,111 constituting a latch section are different from at least one of potentials to be supplied to a word line 105 and supplied to bit lines 106,107; a latch potential control circuit 101 for changing over a normal operation mode and a test mode in accordance with a signal applied to a test mode setting pin 102; and a read/write control circuit 103 for controlling the potentials to be supplied to the sources of the load transistors 108,111 to values lower than that of at least one of potentials to be supplied to the word line 105 and supplied to the bit lines 106,107, at least during the optional period of read-out operation at the test mode. <P>COPYRIGHT: (C)2007,JPO&INPIT |
