发明名称 |
DUAL PORT GAIN CELL WITH SIDE AND TOP GATED READ TRANSISTOR |
摘要 |
A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity. |
申请公布号 |
WO2007023011(A3) |
申请公布日期 |
2007.06.21 |
申请号 |
WO2006EP63581 |
申请日期 |
2006.06.27 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION;IBM UNITED KINGDOM LIMITED;MANDELMAN, JACK;CHENG, KANGGUO;DIVAKARUNI, RAMACHANDRA;RADENS, CARL;WANG, GENG |
发明人 |
MANDELMAN, JACK;CHENG, KANGGUO;DIVAKARUNI, RAMACHANDRA;RADENS, CARL;WANG, GENG |
分类号 |
H01L27/108;H01L21/8242 |
主分类号 |
H01L27/108 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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