发明名称 A/D CONVERSION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To enable high-speed continuous operation by shortening waiting time until restarting a pulse delay circuit in a TAD-type A/D conversion circuit, and further to enable high-speed continuous operation and to reduce a circuit size simultaneously. SOLUTION: Every time when A/D conversion is executed, a pause is inserted for initializing a pulse delay circuit 10 and a round number counter 13, thus enabling numerical data outputted by a latch & encoder 11 and a latch circuit 14 to be used as A/D-converted data as they are. A control signal generation circuit 15 generates a counter initialization signal RC for initializing a start control signal RR for controlling the start/pause of the pulse delay circuit 10, and the round number counter 13. The control signal generation circuit 15 comprises an edge detection circuit composed of a delay circuit 16 and logic circuits 17-19, and can set a pause that is shorter than the period of a sampling block CKS, thus achieving high-speed continuous operation. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007158400(A) 申请公布日期 2007.06.21
申请号 JP20050346510 申请日期 2005.11.30
申请人 DENSO CORP 发明人 WATANABE TAKAMOTO
分类号 H03M1/50;H03K5/04;H03K5/13;H03K5/15;H03K19/0948 主分类号 H03M1/50
代理机构 代理人
主权项
地址