<p>A method and a device for processing instructions. The device (100) includes a pipelined processor (110), an instruction memory unit (120) and a register file (130), whereas the pipelined processor (110) includes a write- back unit (118) and an execution unit (116) . The device (100) is characterized by including a controller (140) that is adapted to receive a first register group size information and a first register identification information that define a first group of source registers associated with a first instruction; and to determine an execution related operation of the first instruction in response to the first register group size information, the first register identification information, a second register group size information and a second register identification information. Whereas the second register group size information and the second register identification information define a second group of target registers associated with a second instruction. Whereas the second instruction is provided to the pipelined processor (110) before the first instruction.</p>
