发明名称 STRAINED SILICON CMOS DEVICE
摘要 PROBLEM TO BE SOLVED: To provide an improved method of controlling a boundary between a compressive and a tensile portion of a dual-stress liner in a semiconductor device. SOLUTION: The boundary may be appropriately designed to be located by a predetermined distance as measured from a PFET feature, such as a boundary of a channel or an active region 301, rather than being determined by an N-well 302 boundary 360, 361, 362, 363. This allows providing an opportunity to improve and/or match the performance of a PFET 350. By appropriately designing the boundary between a compressive portion 305 and a tensile portion of the dual-stress liner, the compressive stress on a PFET can be reduced in the y direction while maintained or increased in the x direction, whereby the performance of the PFET can be improved. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007158322(A) 申请公布日期 2007.06.21
申请号 JP20060307623 申请日期 2006.11.14
申请人 TOSHIBA CORP 发明人 KOYAMA HIROSUKE
分类号 H01L21/8238;H01L27/092;H01L29/78;H01L29/786 主分类号 H01L21/8238
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