发明名称 |
Apparatus and Method for Pipelined Memory Operations |
摘要 |
A semiconductor memory device has a memory core that includes at least eight banks of dynamic random access storage cells and an internal data bus coupled to the memory core. The internal data bus receives a plurality of data bits from a selected bank of the memory core. The semiconductor memory device further comprises a first interface to receive a read command from external to the semiconductor memory device and a second interface to output first and second subsets of the plurality of data bits. The first subset is output during a first phase of an external clock signal and the second subset is output during a second phase of the external clock signal. The first phase includes a first edge transition and the second phase includes a second edge transition. The second edge transition is an opposite edge transition with respect to the first edge transition.
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申请公布号 |
US2007140035(A1) |
申请公布日期 |
2007.06.21 |
申请号 |
US20070675054 |
申请日期 |
2007.02.14 |
申请人 |
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发明人 |
BARTH RICHARD M.;TSERN ELY K.;HOROWITZ MARK A.;STARK DONALD C.;HAMPEL CRAIG E.;WARE FREDERICK A.;DILLON JOHN B.;DILLON NANCY D. |
分类号 |
G11C8/00 |
主分类号 |
G11C8/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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