Duty cycle correction circuit for use in clock generation circuit, has shared charge pump receiving internal clock signals and outputting control signal based on clock signals, where charge pump compensates duty cycle errors

摘要

The circuit (620) has two different amplification parts (625a, 625b) receiving two different pair of intermediate differential clock signals (CLK1/CLKB1, CLK2/CLKB2), and outputting two different pair of internal clock signals. A shared charge pump (630) receives the pair of internal clock signals, and outputs a control signal based on the pair of internal clock signals, where the charge pump compensates duty cycle errors of each of the intermediate differential clock signals. A capacitive element has a capacitor that is connected between nodes. An independent claim is also included for a method for generating a clock signal.