发明名称 NOR FLASH MEMORY CONTROLLING DATA HOLD TIME ACCORDING TO CLOCK FREQUENCY
摘要 A NOR flash memory controlling data hold time according to a clock frequency is provided to satisfy parameter characteristics related with data output regardless of the clock frequency, by controlling the delay time of a clock signal. A NOR flash memory cell(100) includes a memory cell(110). A sense amplifier(120) senses data stored in the memory cell. A data output buffer(140) outputs data sensed by the sense amplifier in response to a clock signal. A clock delay circuit(160) delays an external clock signal, and provides the clock signal to the data output buffer. A delay control circuit(170) controls delay time of the clock delay circuit according to the frequency of the clock signal. The data output buffer controls data hold time of the sensed data in response to the clock signal, and the delay control circuit controls delay time of the clock delay circuit according to a latency value stored in a mode register.
申请公布号 KR100732634(B1) 申请公布日期 2007.06.20
申请号 KR20060015232 申请日期 2006.02.16
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 YOON, CHI WEON
分类号 G11C16/32 主分类号 G11C16/32
代理机构 代理人
主权项
地址
您可能感兴趣的专利