| 摘要 |
<p>Consumption power is reduced in a digital matched filter for determining a correlation value between a digital signal (Io) of 6 bits, which is synchronous with a clock, and a despreading code sequence (C7 C6 C5 C4 C3 C2 C1 C0) which includes 8 despreading codes. First to eighth flip-flop sets (211-218) constituting a storage section (210) are sequentially selected clock by clock by a write selection circuit (220), and the digital signal (Io) is stored in the selected flip-flop set. The 8 despreading codes are stored in first to eighth code flip-flops (231-238), respectively, and are shifted in synchronism with the clock. Output signals of the first to eighth flip-flop sets are multiplied by output signals of the first to eighth code flip-flops in first to eighth multiplication circuits (241-248), respectively.</p> |
