SEMICONDUCTOR MEMORY DEVICE USING WAVE PIPELINE SCHEME

摘要

A semiconductor memory device using a wave pipeline scheme is provided to reduce delay between a second clock signal(CDQi) and a third clock signal(CDQD) caused due to the voltage level variation of EVC/IVC. In a semiconductor memory device using a wave pipeline scheme, a first clocked inverter outputs parallel data input through the wave pipeline scheme, in response to a first clock signal. A first latch stores data output from the first clocked inverter. A level shifter changes the voltage level of the data of the first latch. A second clocked inverter changes the data transferred from the level shifter into serial data in response to a second clock signal. A second latch stores data output from the second clocked inverter. A third clocked inverter receives and outputs the second latched data in response to a third clock signal. A control signal generation circuit(300) generates the first, the second and the third clock signal in synchronization with an external clock inputted from the outside.