| 摘要 |
A method for manufacturing a flash memory device is provided to reduce an interference effect and to improve a coupling ratio by reducing the capacitance between adjacent floating gates using a conductive layer formed in an isolation layer. A first trench is formed on a semiconductor substrate(30) having a tunnel oxide layer(31), a first polysilicon layer(32) and a nitride layer. An isolation layer(34) is formed in the first trench. A second trench is formed in the isolation layer. A bottom portion of the second trench is lower than the tunnel oxide layer. A conductive layer(36) is formed on the resultant structure and polished, so that the conductive layer remains in the second trench alone. The first polysilicon layer is exposed to the outside by removing the nitride layer.
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