发明名称 Digital data driver and display device using the same
摘要 A digital data driver including a receiving unit and a digital-to-analog (D/A) converting unit is provided. The D/A converting unit is used to convert N digital data outputted from the receiving unit into corresponding N analog data. The D/A converting unit includes a grey-level voltage generator and K sub D/A converting units. The grey-level voltage generator provides 2<SUP>M </SUP>grey-level voltages. The i<SUP>th </SUP>sub D/A converting unit includes 2<SUP>M </SUP>buffers and <maths id="MATH-US-00001" num="00001"> <MATH OVERFLOW="SCROLL"> <MROW> <MFRAC> <MI>N</MI> <MI>K</MI> </MFRAC> <MO>⁢</MO> <MROW> <MI>D</MI> <MO>/</MO> <MI>A</MI> </MROW> </MROW> </MATH> </MATHS> converters. In which, each buffer receives and outputs a corresponding grey-level voltage. The j<SUP>th </SUP>D/A converter receives the <maths id="MATH-US-00002" num="00002"> <MATH OVERFLOW="SCROLL"> <MSUP> <MROW> <MO>[</MO> <MROW> <MROW> <MROW> <MO>(</MO> <MROW> <MI>i</MI> <MO>-</MO> <MN>1</MN> </MROW> <MO>)</MO> </MROW> <MO>x</MO> <MFRAC> <MI>N</MI> <MI>K</MI> </MFRAC> </MROW> <MO>+</MO> <MI>j</MI> </MROW> <MO>]</MO> </MROW> <MI>th</MI> </MSUP> </MATH> </MATHS> digital data, and selects and outputs one of the grey-level voltages that passed the buffers as the <maths id="MATH-US-00003" num="00003"> <MATH OVERFLOW="SCROLL"> <MSUP> <MROW> <MO>[</MO> <MROW> <MROW> <MROW> <MO>(</MO> <MROW> <MI>i</MI> <MO>-</MO> <MN>1</MN> </MROW> <MO>)</MO> </MROW> <MO>x</MO> <MFRAC> <MI>N</MI> <MI>K</MI> </MFRAC> </MROW> <MO>+</MO> <MI>j</MI> </MROW> <MO>]</MO> </MROW> <MI>th</MI> </MSUP> </MATH> </MATHS> analog data according to the <maths id="MATH-US-00004" num="00004"> <MATH OVERFLOW="SCROLL"> <MSUP> <MROW> <MO>[</MO> <MROW> <MROW> <MROW> <MO>(</MO> <MROW> <MI>i</MI> <MO>-</MO> <MN>1</MN> </MROW> <MO>)</MO> </MROW> <MO>x</MO> <MFRAC> <MI>N</MI> <MI>K</MI> </MFRAC> </MROW> <MO>+</MO> <MI>j</MI> </MROW> <MO>]</MO> </MROW> <MI>th</MI> </MSUP> </MATH> </MATHS> digital data, where N, K, <maths id="MATH-US-00005" num="00005"> <MATH OVERFLOW="SCROLL"> <MROW> <MFRAC> <MI>N</MI> <MI>K</MI> </MFRAC> <MO>,</MO> </MROW> </MATH> </MATHS> i and j are the positive integers, <maths id="MATH-US-00006" num="00006"> <MATH OVERFLOW="SCROLL"> <MROW> <MN>1</MN> <MO><=</MO> <MI>i</MI> <MO><=</MO> <MROW> <MI>K</MI> <MO>⁢</MO> <MSTYLE> <mspace width="0.8em" height="0.8ex"/> </MSTYLE> <MO>⁢</MO> <MI>and</MI> <MO>⁢</MO> <MSTYLE> <mspace width="0.8em" height="0.8ex"/> </MSTYLE> <MO>⁢</MO> <MN>1</MN> </MROW> <MO><=</MO> <MI>j</MI> <MO><=</MO> <MROW> <MFRAC> <MI>N</MI> <MI>K</MI> </MFRAC> <MO>.</MO> </MROW> </MROW> </MATH> </MATHS>
申请公布号 US7233272(B1) 申请公布日期 2007.06.19
申请号 US20060403341 申请日期 2006.04.12
申请人 NOVATEK MICROELECTRONICS CORP. 发明人 YEN CHIH-JEN
分类号 H03M1/66 主分类号 H03M1/66
代理机构 代理人
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