发明名称 Method and apparatus for reducing memory latency in a cache coherent multi-node architecture
摘要 A method for reducing memory latency in a multi-node architecture. In one embodiment, a speculative read request is issued to a home node before results of a cache coherence protocol are determined. The home node initiates a read to memory to complete the speculative read request. Results of a cache coherence protocol may be determined by a coherence agent to resolve cache coherency after the speculative read request is issued.
申请公布号 US7234029(B2) 申请公布日期 2007.06.19
申请号 US20000749660 申请日期 2000.12.28
申请人 INTEL CORPORATION 发明人 KHARE MANOJ;BRIGGS FAYE A.;KUMAR AKHILESH;LOOI LILY P.;CHENG KAI
分类号 G06F12/08;G06F13/00 主分类号 G06F12/08
代理机构 代理人
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