Semiconductor memory device with MOS transistors each having floating gate and control gate

摘要

A semiconductor memory device includes a memory cell array, word lines, select gate lines, and switch elements. The memory cell array includes a plurality of memory cells arranged in a matrix. Each of the memory cells includes a first MOS transistor having a charge accumulation layer and a control gate and a second MOS transistor which has a drain connected to a source of the first MOS transistor. Each of the word lines connects commonly the control gates of the first MOS transistors in a same row. Each of the select gate lines connects commonly the gates of the second MOS transistors in a same row. The switch elements, in an erase operation, electrically connect the select gate lines to a semiconductor substrate in which the memory cell array is formed.