| 摘要 |
An output stage interface circuit ( 1 ) comprises a main bipolar transistor (Q 1 ) coupling a data output terminal ( 5 ) to a first rail ( 2 ) to which the positive of the power supply voltage (V<SUB>DD</SUB>) is applied, and a substrate diffusion isolated main NMOS transistor (MN 1 ) coupling the data output terminal ( 5 ) to a second rail ( 3 ) which is held at ground. Control signals from a data control circuit ( 6 ) selectively operate the main bipolar transistor (Q 1 ) and the main MOS transistor (MN 1 ) for determining the logic high and low states of the data output terminal ( 5 ) during data output. A back gate ( 23 ) of the main MOS transistor (MN 1 ) is independently configurable, and is selectively and alternately coupleable to one of the second rail ( 3 ) and the data output terminal ( 5 ) in response to the voltage on the data output terminal ( 5 ), so that when the voltage on the data output terminal ( 5 ) is pulled below a voltage reference (V<SUB>REF</SUB>), the back gate ( 23 ) is coupled to the data output terminal ( 5 ) for preventing a parasitic bipolar transistor (Q<SUB>p1</SUB>) and a parasitic diode (D<SUB>p2</SUB>) of the main MOS transistor (MN 1 ) sourcing current to the data bus. First and second primary buffer circuits ( 11 ) and ( 14 ) are coupled between the first rail ( 2 ) and the back gate ( 23 ) of the main MOS transistor (MN 1 ), so that when the voltage on the data output terminal ( 5 ) is pulled below the voltage reference (V<SUB>REF</SUB>), the base ( 13 ) and the gate ( 10 ) of the main bipolar transistor (Q 1 ) and the main MOS transistor (MN 1 ) can be pulled to the voltage on the data output terminal ( 5 ) for maintaining the main bipolar transistor (Q 1 ) and the main MOS transistor (MN 1 ) in the off-state.
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