发明名称 METHOD OF PLATING FOR FILLING VIA HOLES
摘要 A method of plating for filling via holes (14), in which each via hole (14) formed in an insulation layer (12) covering a substrate so as to expose, at its bottom, part of a conductor layer (10) located on the substrate, is plated with copper and filled with the plated metal. The method comprises the steps of forming a copper film (21) on the top surface of the insulation layer (12) covering the substrate, and the side walls and bottoms of the respective via holes (14), immersing the substrate having the copper film (21) formed in an aqueous solution containing a plating promoter to thereby deposit the plating promoter (22) on the surface of the copper film (21), removing the plating promoter (21) from the surface of the copper film located on the insulation layer (12) and leaving the plating promoter (22) on the side walls and bottoms of the respective via holes (14), and subsequently electroplating the substrate with copper (23) to thereby fill the via holes (14) and simultaneously form a continuous copper film (23) which eventually covers the via holes filled with the plated copper as well as the copper film (21) previously formed on the insulation layer (12). The method is suitable for satisfactorily filling via holes (14), having a small diameter and a large aspect ratio, with plated copper. <IMAGE> <IMAGE>
申请公布号 KR100730326(B1) 申请公布日期 2007.06.19
申请号 KR20010004601 申请日期 2001.01.31
申请人 SHINKO ELECTRIC IND CO 发明人 NAKAMURA KENJI;NAKAZAWA MASAO
分类号 H01L21/28;C25D5/18;C25D5/34;C25D7/12;H05K3/18;H05K3/40;H05K3/42;H05K3/46 主分类号 H01L21/28
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