| 摘要 |
A method for manufacturing a flash memory device is provided to improve an interference effect of edge cells adjacent to a selection transistor and to enhance a program speed. An isolation layer is formed on a semiconductor substrate to define an active region and a field region. A tunnel oxide layer and a first polysilicon layer are formed on the entire structure. The first polysilicon layer is patterned to remove a part of a source selection transistor region, a part of an adjacent cell region of the source selection transistor region, a part of a drain selection transistor, and a part of an adjacent cell region of the drain selection transistor. A dielectric layer is formed on the entire structure and a second polysilicon layer is formed thereon. The second polysilicon layer and the dielectric layer are pattern in a line. A cell gate is formed by patterning the first polysilicon layer. A gate is formed on the source selection transistor region and the drain selection transistor region.
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