| 摘要 |
<p>A digital delay cell and a delay line circuit having the same are provided to reduce power consumption and obtain output signals of various phases by improving a duty characteristic and an output signal characteristic of the delay cell and the delay line circuit. A delay line circuit having a digital delay cell includes a plurality of delay cells connected in series. The delay cell includes a first logic gate, a second logic gate, and a third logic gate. The first logic gate generates a signal based on an input signal and transmits the generated signal to a pass terminal in response to a selection signal. The second logic gate generates a signal based on the input signal in response to the selection signal. The third logic gate generates a signal based on any one signal of output signals of the second logic gate and a return signal, and transmits the generated signal to an output terminal.</p> |
