发明名称 SIMULATION-BASED TIMING/FUNCTIONAL DEBUGGING AND VERIFICATION METHOD
摘要 A simulation-based timing/functional debugging and verification method is provided to enhance whole debugging efficiency by effectively performing hardware or software debugging in a high speed actual operation situation of an in-circuit or in-system environment for DUT(Design Under Test) implemented in a programmable or foundry semiconductor. Dynamic information for all or more than one design objects included in a semiconductor design target is collected in real-time in the operation situation operating the semiconductor design target implemented in the programmable or foundry semiconductor mounted on a hardware board. The functional or timing error included in the semiconductor design target is quickly found and corrected by performing the simulation for the collected dynamic information and the design objects in more than one HDL(Hardware Description Language) simulator through simulation compilation/elaboration.
申请公布号 KR20070062399(A) 申请公布日期 2007.06.15
申请号 KR20060092573 申请日期 2006.09.22
申请人 YANG, SEI YANG 发明人 YANG, SEI YANG
分类号 G06F11/28;G06F11/00;G06F11/27;G06F11/273 主分类号 G06F11/28
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