发明名称 |
Partial-via-first dual-damascene process with tri-layer resist approach |
摘要 |
A partial-via-first dual-damascene method using a tri-layer resist method forms a first via hole through partial thickness of a dielectric layer, and forms a tri-layer resist structure on the dielectric layer to fill the first via hole with the bottom photoresist layer. A dry development process is performed to transfer a first opening on the top photoresist layer to the middle layer and the bottom photoresist layer, and expose the first via hole again, and remove the top photoresist layer. A dry etching process is then performed to form a second via hole under the first via hole and a trench over the second via hole. Finally a wet striping process is used to remove the remainder of the photoresist layer.
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申请公布号 |
US2007134917(A1) |
申请公布日期 |
2007.06.14 |
申请号 |
US20050301917 |
申请日期 |
2005.12.13 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
发明人 |
LI TSAI-CHUN;WU TSANG-JIUH;OUYANG HUI |
分类号 |
H01L21/4763 |
主分类号 |
H01L21/4763 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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