| 摘要 |
PROBLEM TO BE SOLVED: To improve ESD resistance of a high withstand voltage MOS transistor. SOLUTION: An n-type lightly doped drift layer 11 is provided so as to cover an n-type heavily doped drain layer 41 from an internal section side of a p-type silicon substrate 100, and an n-type lightly doped drift layer 12 is provided so as to cover an n-type heavily doped source layer 42 likewise. A p-type ESD surge recovery layer 20 is provided at a region deeper than a region where the drift layers 11, 12 are provided, and the layer 20 forms pn junctions with the layers 11, 12. A top contact layer 30 is provided at a region shallower than a region where the layer 20 is provided and is overlapped on the layer 20 in plan view of a substrate surface 101. An ESD surge current applied to an electrode 81 flows in the layer 41, is introduced to the layer 20 by avalanche breakdown at the pn junctions constituted by the layer 11 and the layer 20, and is recovered to an electrode 83 through the layer 30. COPYRIGHT: (C)2007,JPO&INPIT
|
