| 摘要 |
A high-reliability, multi-threshold complementary metal oxide semiconductor (CMOS) latch circuit having low sub-threshold leakage current is provided. More particularly, a latch circuit and flip-flop that can be applied in the deep sub-micron era and that are entirely configured of only CMOS using a combination of a high threshold device and a low threshold device and a low-threshold-voltage stack structure, without using a power gating technique such as multi-threshold CMOS (MTCMOS) and a back bias voltage control technique such as variable threshold CMOS (VTCMOS), are provided. The multi-threshold latch circuit includes: a forward clock inverter including a low threshold transistor only and inverting an input-terminal logic state and applying the inverted logic state to an output-terminal logic state when a clock is in a first logic state; and a backward clock inverter including a high threshold transistor, forming a circular latch structure together with the forward clock inverter, and inverting an input-terminal logic state and applying the inverted logic state to an output logic state when the clock is in a second logic state.
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