发明名称 Memory buffering with fast packet information access for a network device
摘要 A networking device employing memory buffering in which a first memory is logically configured into blocks, and the blocks are logically configured into particles, where a second memory is configured to mirror the first memory in which a fixed number of bits in the second memory are allocated for each particle in the first memory so that scheduling and datagram lengths of packets stored in the first memory may be stored in the second memory. Other embodiments are described and claimed.
申请公布号 US2007133581(A1) 申请公布日期 2007.06.14
申请号 US20050298965 申请日期 2005.12.09
申请人 CISCO TECHNOLOGY, INC. 发明人 MA SHA;COHEN EARL T.
分类号 H04L12/56;H04L12/28 主分类号 H04L12/56
代理机构 代理人
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