| 摘要 |
A core memory unit is disclosed using double card modules with each module having an X wire system common to both cards, and further having several Y wire systems, one per bit position (bit plane). The module holds decoders for X and Y wire systems, driven by a predecoder system common to all modules and external thereto. The Y wire systems operate with anticoincidence, the sense wire system is a double wire system, each wire being rectangularly looped as threaded through half of the cores of the bit locations of each bit position to suppress noise.
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