发明名称 Method for testing semiconductor integrated circuit and method for verifying design rules
摘要 Not only defects in DC characteristics and a degeneracy fault but defects in AC characteristics such as SI faults (a crosstalk faults and an IR-DROP fault) and a delay fault, which tend to increase as design rules become finer in recent years, are detected as a measure used when the finished quality of a semiconductor integrated circuit is evaluated. The defects in the AC characteristics are detected by utilizing a scan path circuit provided to detect the degeneracy fault in the semiconductor integrated circuit, bringing scan chains to states in which shift resistor operations can be effected for the input of patterns by which a glitch fault and the IR-DROP fault between the scan chains can be detected, and not only utilizing variations in power supply voltage fed to the semiconductor integrated circuit and in signal voltage inputted to scan-in terminals but also varying the frequency of the test patterns.
申请公布号 US2007136629(A1) 申请公布日期 2007.06.14
申请号 US20060445195 申请日期 2006.06.02
申请人 NOBEKAWA TOMOKO 发明人 NOBEKAWA TOMOKO
分类号 G01R31/28 主分类号 G01R31/28
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