| 摘要 |
A power semiconductor device having reduced on-resistance (R<SUB>on</SUB>) and a method of manufacturing the same is provided. The method is provided after forming the gate region for inclinedly implanting the dopant of the first conductivity type into the JFET region above the epitaxial layer. The gate region blocks the dopant from entering the channel region, thus the dopant is not directly implanted into the channel region. Furthermore, the breakdown voltage and the threshold voltage in the channel region will not be affected by increasing the quantity of dopant into the JFET region in the ion implantation, thereby achieving a decrease in the on-resistance of the DMOS structure.
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