发明名称 Method for voltage controlled oscillator yield enhancement
摘要 A method of selecting fabrication parameters for an on-chip inductor of an integrated circuit. The integrated circuit includes a capacitor fabricated prior to the inductor. The capacitance of the capacitor is measured and, based on the measured capacitance and on a desired frequency range, a suitable inductor is fabricated. The integrated circuit may include a voltage controlled oscillator (VCO), and the selection of the fabrication parameters of the inductor includes the selection of a lithography mask for the fabrication of the inductor for maximizing yield across the wafer. Therefore, the integrated circuit can have exactly one VCO for covering the desired frequency range, as opposed to at least two VCO's with overlapping frequency ranges, thereby saving significant silicon area and increasing the yield per wafer.
申请公布号 US2007132520(A1) 申请公布日期 2007.06.14
申请号 US20050296536 申请日期 2005.12.08
申请人 SIRIFIC WIRELESS CORPORATION 发明人 BELLAOUAR ABDELLATIF
分类号 H03B5/08 主分类号 H03B5/08
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