发明名称 Access control apparatus, access control system, processor, access control method, memory access control apparatus, memory access control system, and memory access control method
摘要 An access control apparatus includes a parity generator that generates a parity for original data to be written into a memory; and a parity adder that generates parity-added data by adding the parity to the original data; a first syndrome generator that generates a first syndrome of first mask data to mask the parity-added data. The first syndrome is a value associated beforehand with a first access code to be used when a writer accesses the memory. The apparatus also includes a first mask generator that generates the first mask data based on the first syndrome, the first access code, and a first memory address; a first XOR unit that obtains first post-operation data by calculating an XOR between the parity-added data and the first mask data; and a writing unit that writes the first post-operation data into the memory.
申请公布号 US2007136647(A1) 申请公布日期 2007.06.14
申请号 US20060519797 申请日期 2006.09.13
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 KANAI TATSUNORI;YOSHII KENICHIRO
分类号 H03M13/00 主分类号 H03M13/00
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