发明名称 DIGITALER BREITBAND-PHASENREGELKREIS (PLL) MIT HALBFREQUENZAUSGANG
摘要 <p>A digital phase locked loop includes an automatic gain control that applies a gain to an input signal in order to provide a gain controlled signal. A 90° phase shifter applies a 90° phase shift to the gain controlled signal in order to provide a 90° phase shifted version of the gain controlled signal. A phase detector is driven by the gain controlled signal, by the 90° phase shifted version of the gain controlled signal, and by sinusoidal and co-sinusoidal signals. A loop filter integrates an output of the phase detector and provide servo equalization for the phase-locked loop. A digital dual frequency oscillator has a fundamental frequency controlled by an output signal from the loop filter. Also, the digital dual frequency oscillator generates the sinusoidal and co-sinusoidal signals.</p>
申请公布号 DE60219930(D1) 申请公布日期 2007.06.14
申请号 DE2002619930 申请日期 2002.08.22
申请人 HONEYWELL INTERNATIONAL INC. 发明人 WHITE, STANLEY A.
分类号 H03L7/08;G01C19/56;G01C21/16 主分类号 H03L7/08
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