发明名称 Memory module e.g. dynamic RAM, for storing data, has effective bits and parity bits for error correction, and set of rank groups, where individually assigned parity bit-memory module for each rank group is provided
摘要 <p>The module has effective bits and parity bits for error correction. A set of memory modules is provided, where all effective bit memory modules are summarized in a rank. A group of bits in parallel form is provided for each memory module. A set of rank groups (RG0) is provided, and an individually assigned parity bit-memory module (MP1) for each rank group is provided. An effective bit lane is provided for transmission of bit packets.</p>
申请公布号 DE102005053625(A1) 申请公布日期 2007.06.14
申请号 DE20051053625 申请日期 2005.11.10
申请人 INFINEON TECHNOLOGIES AG 发明人 RUCKERBAUER, HERMANN
分类号 G11C29/52 主分类号 G11C29/52
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