| 摘要 |
<p>A semiconductor component having electrode terminals 14 formed in rectangular planar shapes arranged in parallel on an electrode forming surface of a semiconductor chip and formed with rerouting patterns 16 electrically connected with the electrode terminals 14 through vias on the surface of an electrical insulating layer covering the electrode forming surface, characterized in that the planar arrangement of the via pads 20 formed on the surface of the electrical insulating layer is made an arrangement alternately offset to one side and the other side of the longitudinal direction of the electrode terminals 14 and in that rerouting patterns 16 are provided connected to the via pads 20 . The present invention enables easy formation of rerouting patterns even when the electrode terminals are arranged at fine intervals.</p> |
