发明名称 |
High-speed multiplexer latch |
摘要 |
Embodiments of a high-speed multiplexer latch are described. The multiplexer latch may include a multiplexer and a latch coupled to each other at a first node and a second node. The multiplexer latch may further include an inverter having an input and an output. The input of the inverter is also coupled to the latch at the second node and the output of the inverter is coupled to a data output terminal. The multiplexer latch may further include a bypass circuit coupled to the latch at the first node and the data output terminal.
|
申请公布号 |
US7230856(B1) |
申请公布日期 |
2007.06.12 |
申请号 |
US20050259342 |
申请日期 |
2005.10.24 |
申请人 |
CYPRESS SEMICONDUCTOR CORPORATION |
发明人 |
VENUGOPAL RAJESH;LANDRY GREG J.;PENG TAO |
分类号 |
G11C7/00 |
主分类号 |
G11C7/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|