发明名称 |
Efficent column redundancy techniques |
摘要 |
The present invention relates to a system and method adapted to increase memory cell and memory architecture design yield. The present invention includes memory architecture having a decoder and a multi-bank memory. The decoder is adapted to decode addresses. The multi-bank memory interacts with the decoder, wherein the multi-bank memory includes at least one output data bit adapted to complete a word for a failing bank in the multi-bank memory.
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申请公布号 |
US7230872(B2) |
申请公布日期 |
2007.06.12 |
申请号 |
US20050064218 |
申请日期 |
2005.02.23 |
申请人 |
BROADCOM CORPORATION |
发明人 |
WINOGRAD GIL I.;TERZIOGLU ESIN |
分类号 |
G11C29/28;G06F13/40;G11C7/18;G11C11/419;G11C29/00 |
主分类号 |
G11C29/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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