A method for planarizing a semiconductor device is provided to improve the step coverage of a semiconductor wafer by preventing a metal interconnection from being exposed in a CMP process for planarizing an insulation layer on the metal interconnection. A metal interconnection is formed on a semiconductor substrate(110). A hard mask layer pattern(145) is formed on the metal interconnection. The metal interconnection is etched to form a metal interconnection pattern(120a) by using the hard mask layer pattern. The front surface of the resultant structure is covered with an insulation layer. The insulation layer is planarized by a CMP process. The hard mask layer pattern is made of a material having etch selectivity with respect to the insulation layer. The hard mask layer pattern can be made of a silicon nitride layer or a dual layer of a silicon oxide layer and a silicon nitride layer.
