| 摘要 |
A semiconductor integrated circuit for performing processing relating to a test of a plurality of memory units provided therein while suppressing an increase of a circuit area is provided, wherein testing input data generated in a testing circuit is shifted successively on registers of a first data shift circuit formed by scan flip-flops and transferred to each memory unit when carrying out a test on a plurality of memory units, and testing output data in accordance with the testing input data is shifted successively on registers of a second data shift circuit formed by using scan flip-flops and retrieved by the testing circuit.
|
