| 摘要 |
A scan flip-flop circuit and related scan chain are disclosed. The scan flip flop comprises in one embodiment an input stage receiving, selecting between, and outputting either a normal logic signal or a scan logic signal in accordance with an operation mode for the scan flip-flop circuit. The scan flip-flop further comprises a flip-flop receiving either the normal logic signal or the scan logic signal selected by the input stage, and outputting in accordance with a clock signal a first logic signal from a first flip-flop output terminal and an output stage receiving the first logic signal and comprising first and second output terminals, such that a signal output from the first output terminal is identical to the normal logic signal received in the input stage, and a signal output from the second output terminal maintains a high logic value when the scan flip-flop circuit operates in a normal mode and a signal output from the first and second output terminals are identical to the scan logic signal received in the input stage when the scan flip-flop circuit operates in a scan mode.
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