| 摘要 |
A method for performing a built-in and at-speed test in a system-on-chip includes receiving a statistic timing analysis report of the system-on-chip, determining a plurality of critical paths for an at-speed test in the system-on-chip according to the statistic timing analysis report, analyzing signals at observe control points and capture control points of each of the critical paths for generating a plurality of test states, and transmitting the test states to a virtual instrumentation software architecture wrapper.
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