发明名称 |
Method and apparatus for high speed testing of latch based random access memory |
摘要 |
A method and apparatus for testing latch based random access memory includes steps of generating a scan enable signal for testing latch based random access memory and generating a scan clock signal for testing the latch based random access memory wherein the scan clock signal has a first scan clock period for a shift cycle and a second scan clock period for a capture cycle.
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申请公布号 |
US7231563(B2) |
申请公布日期 |
2007.06.12 |
申请号 |
US20040901609 |
申请日期 |
2004.07.28 |
申请人 |
LSI CORPORATION |
发明人 |
VINKE DAVID;BALAJI EKAMBARAM |
分类号 |
G11C29/00;G01R31/28;G11C29/32 |
主分类号 |
G11C29/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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