发明名称 Delay line for a ring oscillator circuit
摘要 A delay line for a ring oscillator circuit includes at least one delay stage having a multiple logic gate delay cells driven by a multiplexer. The multiplexer is symmetrically configured and includes multiple logic gates that are similar to the logic gates of the delay stage.
申请公布号 US7230498(B2) 申请公布日期 2007.06.12
申请号 US20050112746 申请日期 2005.04.22
申请人 STMICROELECTRONICS S.R.L. 发明人 OSVALDELLA MAURO
分类号 H03B27/00;H03B1/00;H03K3/03;H03K5/00;H03K5/13 主分类号 H03B27/00
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