| 摘要 |
A method for reducing retention flip-flop using register-transfer level modeling and simulation of MTCMOS(multi-threshold complementary metal oxide semiconductor) circuit is provided to decrease the number of used retention flip-flops as compared with a conventional MTCMOS circuit by selectively using the retention flip-flop in the MTCMOS circuit. Blocks using a retention flip-flop and blocks using a general flip-flop are divided in an MTCMOS circuit(11). An original register-transfer level code with respect to predetermined blocks is received to generate an MTCMOS simulation model(12). The MTCMOS simulation model can include a model of the retention flip-flop and a model of the general flip-flop. A simulation of a register-transfer level is carried out by using the register-transfer level code. As a result of the simulation, the division process is repeated if a different operation from the register-transfer level code is performed. As a result of the simulation, a synthesis script is generated with respect to the blocks using the retention flip-flop and the blocks using the general flip-flop if the same normal operation as the register-transfer level code is performed(15). A logic synthesis is performed by using the register-transfer level code(16).
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