APPARATUS AND METHOD FOR OPTIMIZING LOOP BUFFER IN RECONFIGURABLE PROCESSOR

摘要

A device and a method for optimizing a loop buffer in a reconfigurable processor are provided to offer the reconfigurable processor not performing a delay operation in each circuit unit by using a memory storing information calculating validity to reduce access overhead and size of the loop buffer. A configuration memory(520) stores configuration bits for configuring at least one loop buffer. A validity information memory(530) stores bit information indicating whether the operations present in a loop are the delay operation. A processing unit(510) determines whether the operation corresponding to a next cycle is the delay operation by referring to bit information received from the validity information memory, and selectively changes and executes the configuration according to the configuration bits received from the configuration memory depending on a determination result. The processing unit includes the loop buffer(512), a delay controller(513), and a processing element(511). The loop buffer selectively outputs the configuration bits according to signals generated in the controller, and the processing unit changes and executes the configuration.