发明名称 Control circuit for self-compensating delay chain for multiple-data-rate interfaces
摘要 Circuits, methods, and apparatus that prevent control signals from changing state while the control signals are being used to delay a read strobe signal. An exemplary embodiment of the present invention provides a control circuit that provides a plurality of control bits to a delay line, where the delay line delays or phase shifts a read strobe signal a duration, where the duration depends on the state of the control bits. The delayed read strobe signal is used to clock one or more data registers. To avoid undesired changes in the duration that the read strobe signal is delayed, the control bits are retimed before being provided to the delay line. A specific embodiment waits for an edge of the strobe signal to be output by the delay line before providing the control bits to the delay line. Another specific embodiment waits until no edge of the strobe signal is being delayed by the delay line before providing the control bits to the delay line.
申请公布号 US7231536(B1) 申请公布日期 2007.06.12
申请号 US20040799408 申请日期 2004.03.12
申请人 ALTERA CORPORATION 发明人 CHONG YAN;SUNG CHIAKANG;HUANG JOSEPH;PAN PHILIP
分类号 G06F1/12;G06F1/04;G06F13/42 主分类号 G06F1/12
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