发明名称 |
INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME |
摘要 |
<p>An integrated circuit is provided to avoid a punch-through by forming a pocket region in a position deeper than an LDD(lightly doped drain) region in a depletion-type transistor of an integrated circuit. A well region including impurities of the first conductivity type is formed in a semiconductor substrate(1). An enhancement-type MOS transistor having a channel region under a gate electrode and a plurality of depletion-type MOS transistors are formed in the well region. At least one of the depletion-type MOS transistor has an implantation region(4a,5a) in the channel region wherein impurities of the second conductivity type are implanted into the implantation region to adjust a threshold voltage. The implantation region has impurities of the first conductivity type and the second conductivity type. The density of the impurities of second conductivity type is higher than that of the impurities of the first conductivity type. The channel region can have a pocket implantation region(10) of the first conductivity type formed under the implantation region. The impurities of the second conductivity type are implanted into a position shallower than that of the pocket implantation region.</p> |
申请公布号 |
KR20070059960(A) |
申请公布日期 |
2007.06.12 |
申请号 |
KR20060116129 |
申请日期 |
2006.11.23 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
SETO CHINATSU;UCHIDA MIKIYA;MIMURO KEN;KANAZAKI EMI |
分类号 |
H01L29/78;H01L21/336 |
主分类号 |
H01L29/78 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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