| 摘要 |
A duty checking circuit of an internal clock is provided to implement a high speed operation by checking a twisted direction and amplitude of a clock duty generated in a semiconductor device and then outputting the checking result to a data pin by sensing first and second internal clock signals using a test mode. A first clock buffer part(10) generates a first internal clock signal synchronized to a rising edge by buffering a clock signal inputted from the outside. A second clock buffer part(20) is enabled by a test mode signal, and generates a second internal clock signal synchronized to a falling edge by buffering the clock signal. A clock duty sensing part(30) compares the first internal clock signal with the second internal clock signal and then outputs the corresponding result, when the test mode signal is enabled. |
