| 摘要 |
A wafer level package and its manufacturing method are provided to intensify a power line and to embody the device having high integration and speed by forming a power plane in the wafer level package itself using a multilayer structure in a pad rerouting process. First and second bonding pads(22a,22b) are arranged on a center portion of a semiconductor chip(21) in two rows. A first insulating layer(23) for exposing the first and second bonding pads to the outside is formed on the chip. A connection line is formed on the first insulating layer to contact the first bonding pad. A power plane(24b) is formed at an outer portion of the second bonding pad. A second insulating layer(25) is formed on the first insulating layer including the connection line and the power plane. At this time, a portion of the connection line and the second bonding pad are exposed to the outside through the second insulating layer. A metal line(26) is formed on the second insulating layer to contact the exposed connection line portion and second bonding pad. A third insulating layer(27) for exposing partially the metal line to the outside is formed thereon. |
