| 摘要 |
An ultra high voltage MOS transistor device includes a gate laterally extending onto a first dielectric layer having a void under the gate edge, and a second dielectric layer covering the gate and the first dielectric layer while retaining the void. The first dielectric layer may be in a form of a field oxide layer or a shallow trench isolation, and a thickness increasing dielectric layer may be further stacked on the field oxide layer or the shallow trench isolation. The thickness increasing dielectric layer may comprise a low dielectric constant material or the shallow trench isolation may be filled with porous oxide material, and then the first dielectric layer may not have the void. In the ultra high voltage MOS transistor device, the vertical electric field occurring nearby the gate edge is relatively low.
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