发明名称 Method and apparatus for improving breakdown voltage of integrated circuits formed using a dielectric layer process
摘要 A method and apparatus for depositing a dielectric layer. The apparatus includes a semiconductor processing chamber configured for use in a dielectric layer deposition process, the semiconductor processing chamber being associated with at least a length, a width, a height, and a volume, one or more gas sources containing one or more gases used in the barrier layer deposition process, and one or more gas flow controllers coupled to the one or more gas sources, the one or more gas flow controllers configured to provide one or more controlled amounts of one or more gas flows to the semiconductor processing chamber during semiconductor processing. One or more gas lines coupled to the one or more gas flow controllers for receiving one or more gas flows from the one or more gas flow controllers, and a pumping system is coupled to the semiconductor processing chamber, the pumping system configured to remove a quantity of gas from either the semiconductor processing chamber or the one or more gas lines. A 3-way valve is coupled to the pumping system and the process chamber, the 3-way valve being configured to allow the one or more gas flows to be sent to the pumping system or to the process chamber.
申请公布号 US2007128860(A1) 申请公布日期 2007.06.07
申请号 US20050320871 申请日期 2005.12.28
申请人 SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION 发明人 HOU KUAN C.;LAN SHOU L.;DONG RUI;ANG TING C.
分类号 H01L21/44;C23C16/00 主分类号 H01L21/44
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