发明名称 |
HARDWARE ACCELERATION SYSTEM FOR SIMULATION OF LOGIC AND MEMORY |
摘要 |
A hardware-accelerated simulator includes a storage memory and a program memory that are separately accessible by the simulation processor. The program memory stores instructions to be executed in order to simulate the chip. The storage memory is used to simulate the user memory. Since the program memory and storage memory are separately accessible by the simulation processor, the simulation of reads and writes to user memory does not block the transfer of instructions between the program memory and the simulation processor, thus increasing the speed of simulation, hi one aspect, user memory addresses are mapped to storage memory addresses by adding a fixed, pre-determined offset to the user memory address. Thus, no address translation is required at run-time. |
申请公布号 |
WO2007064716(A2) |
申请公布日期 |
2007.06.07 |
申请号 |
WO2006US45706 |
申请日期 |
2006.11.29 |
申请人 |
LIGA SYSTEMS, INC.;VERHEYEN, HENRY, T.;WATT, WILLIAM |
发明人 |
VERHEYEN, HENRY, T.;WATT, WILLIAM |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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