发明名称 |
Variably delayable transmission of packets between independently clocked source, intermediate, and destination circuits while maintaining orderly and timely processing in one or both of the intermediate and destination circuits |
摘要 |
In a system having independently-clocked job-performing circuits (e.g., payload processors) and independently-clocked job-ordering circuits (e.g., request and payload suppliers), coordinating mechanisms are provided for coordinating exchanges between the independently-clocked circuits. The coordinating mechanisms include those that use transmitted time-stamps for scheduling contention-free performances within the job-performing circuits of requested jobs. The coordinating mechanisms additionally or alternatively include static and dynamic rate constraining means that are configured to prevent a faster-clocked one of the independently-clocked circuits from overwhelming a more slowly-clocked other of the independently-clocked circuits. In one implementation, independently-clocked telecommunication-shelves house a distributed set of line cards and switch cards. An asynchronous interconnect is provided between the independently-clocked shelves for carrying job requests and payload data between the distributed line cards and the distributed switch cards. The multi-shelf system is scalable and robust because additional or replacement line and switch cards may be inserted into one or another of the independently-clocked shelves as desired and because a unified clock-tree is not needed for synchronizing activities within the interconnected, but independently clocked shelves. |
申请公布号 |
US2007130246(A1) |
申请公布日期 |
2007.06.07 |
申请号 |
US20070699737 |
申请日期 |
2007.01.29 |
申请人 |
LAU ONCHUEN DARYN;ORNES MATTHEW D;BERGEN CHRIS D;DIVIVIER ROBERT J;CHUI GENE K;NORRIE CHRISTOPHER I;CHUI KING-SHING FRANK |
发明人 |
LAU ONCHUEN (DARYN);ORNES MATTHEW D.;BERGEN CHRIS D.;DIVIVIER ROBERT J.;CHUI GENE K.;NORRIE CHRISTOPHER I.;CHUI KING-SHING (FRANK) |
分类号 |
G06F15/16 |
主分类号 |
G06F15/16 |
代理机构 |
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