发明名称 Analog layout module generator and method
摘要 In a computer implemented method of device layout in an integrated circuit design an array having a plurality of cells is selected and stored in a memory of a computer. A schematic view of a plurality of interconnected circuit devices of a circuit is displayed on the computer's display. One or more of the circuit devices of the displayed schematic view are selected by a user. Responsive to the selection of each circuit device, a processing means of the computer populates an empty cell of the array in the memory of the computer with a corresponding layout instance of the circuit device, wherein each layout instance represents a physical arrangement of material(s) that form the corresponding selected circuit device.
申请公布号 US2007130553(A1) 申请公布日期 2007.06.07
申请号 US20050295268 申请日期 2005.12.06
申请人 CADENCE DESIGN SYSTEMS, INC. 发明人 WANG ZHIGANG;FALLON ELIAS;COLWELL REGIS R.
分类号 G06F17/50 主分类号 G06F17/50
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